In modern communications systems, the calibration and tuning of equipment containing RF circuitry normally requires expensive measurement and test equipment. In addition, the testing of RF circuitry can also require considerable time and slow the production flow. This expensive RF testing equipment is often controlled by additional external processing equipment such as a PC. Accordingly, all this external testing and processing equipment typically requires considerable communications and a corresponding lag time between the RF circuitry being tested, the measurement equipment and the PC. Such external testing equipment is also known as Automated Test Equipment (ATE).
One disadvantage of using such standard external test modes is that the test system must test the devices interactively. Consequently, only a limited number of devices can be tested at a given time, and a significant amount of overhead time is incurred due to tester limitations, for example, power up time is needed on certain pins while the mode is being accessed and while the tester is controlling the chip and checking the results. Further, the additional device pins that are to be accessed externally, typically need to be made large because of external connection requirements, and therefore occupy additional circuit/chip area.
Improvements in semiconductor processes, however, are making possible integrated circuits of increasing size and complexity. The semiconductor processing technologies that produce these integrated circuits have advanced to the point where complete systems, including RF circuits, can now be reduced to a single integrated circuit or application specific integrated circuit (ASIC) device. These integrated circuit “die” or “chips” may use many functions that previously could not be implemented on a single die.
If a device or circuit is embedded within an ASIC, built-in self-test (BIST) may be considered the most practical and efficient test methodology and is becoming increasingly popular with semiconductor manufacturers. BIST allows timely testing of the embedded device with a reasonably high degree of fault coverage, without requiring continual interactive (sequential) control via external test equipment.
BIST refers in general to any test structure and/or technique in which the testing algorithm or testing sequences (or test vectors) are generated internal to a device-under-test (DUT) such as a discrete device, an integrated circuit, or ASIC device. The testing algorithm used in BIST may be generally implemented in embedded circuitry of the device, wherein the test vectors are applied to the DUT to determine if the DUT is performing as designed. BIST can be used to test integrated circuits located anywhere on the device.
Unlike external testing approaches, at-speed testing utilizing BIST is readily achieved. BIST also alleviates the need for long and convoluted test vectors and may even function as a surrogate for functional testing. Since the BIST structures generally exist and remain active throughout the life of the device, BIST can be employed at the board or system level to reduce system testing costs, reduce device rejects during production, and to reduce field diagnostic costs. Alternately, BIST structures may be used at the wafer level or within the scribe line areas, which are then usually separated from the tested device.
Accordingly, there is a continued need to improve RF circuit testing and calibration methods utilizing faster and more cost-effective self-calibration circuits and methods.